Serial data communication between two link partners in a digital communication system may be accomplished according to the general configuration of FIG. 1. FIG. 1 is a block diagram illustrating a conventional digital communication link 100 having a transmitter side 101 and a receiver side 102. The transmitter side 101 may include an encoder 103, a multiplexer (MUX) 104, and a modulator 105. The receiver side 102 may include a demodulator 106, a demultiplexer (DEMUX) 107, and a decoder 108. The transmitter side 101 and the receiver side 102 may be coupled by a link infrastructure 110. Alternatively, the link infrastructure may be a loopback path. Notwithstanding, the link infrastructure 110 may be, for example, shielded twisted pair, unshielded twisted pair (UTP), copper wire, or optical fiber or wireless
Typically, the encoder 103 may be adapted to accept raw data bytes from an upstream component or entity of the digital communication system. The raw data bytes may be 4-bit, 8-bit, 16-bit, 32-bit or 64-bit words, for example, and may have been previously encrypted by an upstream component or entity of a digital communication system or the communication link 100. Prior encryption of the 8-bit words may ensure data integrity while the encrypted data traverses the digital communication link 100. Notwithstanding, the coded words may be coded in a manner specially designed to provide reliable transmission over the digital communication link 100.
The encoder 103 may encode each of the 8-bit words into a coded word having n bits. Generally, n is greater than eight (8) bits (n>8). Encoding the 8-bit words may generally be achieved by translating each 8-bit byte of data into a specially coded word having n bits where n is generally greater than eight (8). For example, for Gigabit Ethernet encoding, n is equal to ten (10). The additional (n−8) bits of data provide additional transmission overhead. The increased number of bits resulting from encoding may also provide data redundancy, which is typically utilized for error detection. In addition to the encoding of data words, the additional bits may also be encoded to form control words. Standardized coding such as 3B4B, 5B6B or 8B10B coding are typically utilized to ensure data integrity and transmission reliability.
Once the encoder 103 has encoded the raw data bytes, the resulting coded data 111a may be multiplexed into a serial bitstream 109a by the multiplexer 104. The resulting coded data 111a may also be converted a plurality of serial bit streams as in XAUI where 4 parallel lanes are utilized. The resulting multiplexed serial bitstream 109a may subsequently be transferred to the modulator 105 for processing. The modulator 105 may perform digital-to-analog conversion on the serial bitstream 109a, resulting in an equivalent or corresponding bitstream 109b. The resulting analog serial bitstream 109b may be transferred to the receiver side 102 via the link infrastructure or loopback 110.
The demodulator 106 on the receiver side 102 may be adapted to receive the analog serial bitstream 109b transferred from the transmitter side 101. The demodulator 106 may perform an analog-to-digital conversion on the received serial bitstream 109b, resulting in a serial digital bitstream 109c. The resulting serial digital bitstream 109c generated by the demodulator 106 may be transferred to the demultiplexer 107 for processing. The demultiplexer 107 may be configured to demultiplex the serial digital bitstream 109c by executing the opposite of the multiplexing function performed by multiplexer 104.
The demultiplexer 107 may translate the serial bitstream 109c back into a datastream 111b containing n-bit coded words. For example, in the case of gigabit Ethernet, the demultiplexer 107 may translate the serial bitstream 109c back into 10-bit coded words. The n-bit coded words produced by the demultiplexer 107 may subsequently be transferred to the decoder 108 for processing. The decoder 108 may be adapted to execute the opposite of the encoder function performed by the encoder 103. In this regard, the decoder 108 may convert the n-bit coded words back into 8-bit unencoded bytes. These 8-bit unencoded bytes, if previously encrypted, may be decrypted by an upstream component of the digital communication link 100, for example.
Some coding schemes such as 3B4B, 5B6B and 8B10B encoding, utilize a concept referred to as running disparity (RD). Running disparity refers to the sign, whether positive (+) or negative (−), of a running digital sum (RDS) value. The running digital sum value may represent the running sum of the encoded bits used to represent unencoded data. Typically, logic one (1) may be represented by a positive one (+1) and a logic zero (0) may be represented by a negative one (−1). The running disparity and running digital sum are used in encoding to minimize the DC component of the transmitted coded words on the digital communication link 100.
For example, the 8B10B code is an encoding scheme that translates 8-bit bytes into 10-bit coded words using the running disparity. Some of the features provided by the 8B10B coding scheme may include DC balance, a maximum run length of 5, a maximum RDS of 3, a transition density of 3 to 8 transitions per 10-bit code group, separate code groups for control signaling, and a comma for synchronization of code groups. Below is a standardized 8B10B table that illustrates exemplary data code groups and their corresponding RD(−) and RD(+) translations. The first column of the table, referred to as the code group name, contains data values to be encoded. The second column of the table represents corresponding octal values for the data values to be encoded. The third column of the table represents corresponding byte bits values for the data values to be encoded. The fourth column represents the corresponding encoded (RD−) values for the data values that were to be encoded. Finally, the fifth column represents the encoded (RD+) values for the data values that were to be encoded.
Code-GroupByteByte BitsRD (−)RD (+)NameValueHGF EDCBAabcdei fghjabcdei fghjD0.000000 00000100111 0100011000 1011D1.001000 00001011101 0100100010 1011D2.002000 00010101101 0100010010 1011...............D0.120001 00000100111 1001011000 1001D1.121001 00001011101 1001100010 1001D2.122011 00010101101 1001010010 1001...............D0.240010 00000100111 0101011000 0101D1.241010 00001011101 0101100010 0101D2.242010 00010101101 0101010010 0101...............D0.360011 00000100111 0011011000 1100D1.361011 00001011101 0011100010 1100D2.362011 00010101101 0011010010 1100...............D0.480100 00000100111 0010011000 1101D1.481100 00001011101 0010100010 1101D2.482100 00010101101 0010010010 1101...............D0.5A0101 00000100111 1010011000 1010D1.5A1101 00001011101 1010100010 1010D2.5A2101 00010101101 1010010010 1010...............D0.6C0110 00000100111 0110011000 0110D1.6C1110 00001011101 0110100010 0110D2.6C2110 00010101101 0110010010 0110...............D0.7E0111 00000100111 0001011000 1110D1.7E1111 00001011101 0001100010 1110D2.7E2111 00010101101 0001010010 1110...............D31.7FF111 11111101011 0001010100 1110
FIG. 2 is an encoder system 200 that may be utilized for generating standardized 8B/10B encoding as illustrated in the table above. Referring to FIG. 2, the encoder system 200 may include an input byte bit block 202, an input byte bit label block 204, a 3B4B encoder block 206, a 4B5B encoder block 208, an output code-group bit label block 210 and an encoded output code-group block 212. Input byte bit label block 204 illustrates the arrangement or mapping of the input byte bits corresponding to the input byte bit block 202. Accordingly, input bit 0 corresponds to A, input bit 1 corresponds to B, input bit 2 corresponds to C, input bit 3 corresponds to D, input bit 4 corresponds to E, input bit 5 corresponds to F, input bit 6 corresponds to G, and input bit 7 corresponds to H.
Input byte bits A, B, C, D and E are routed to the input of the 5B6B encoder bock 208 and input byte bits F, G and H are routed to the input of the 3B4B encoder block 206. The output encoded bits generated by the encoder block 208 includes output code group bits a, b, c d, e and i. The output encoded bits generated by the encoder block 206 includes output code group bits f, g, h and j. The byte code-groups bits in the output code-group bit label block 210 are mapped to corresponding bits in the encoded output code-group block 212. Accordingly, output bit a corresponds to 0 output bit b corresponds to 1 output bit c corresponds to 2 output bit d corresponds to 3 output bit e corresponds to 4 output bit i corresponds to 5 output bit f corresponds to bit 6, output bit g corresponds to 7 output bit h corresponds to 8 output bit j corresponds to 9. Accordingly, the encoder system 200 encodes an 8-bit input to the input byte bit block 202 into a corresponding 10-bit output at the encoded output code-group block 212.
The encoder system 200 of FIG. 2 utilizes a 5B6B sub-block and a 3B4B sub-block to generate the 8B10B code. In this regard, a 5B6B code table and a 3B4B code may be utilized to generate an 8B10B code table similar the table above. Each of the 5B6B and 3B4B tables may have an current RD(−) column and a current RD(+) column. The current RD may refer to a state of the RD at the end of a last sub-block. Various rules may be implemented to generate the encoded 8B10B code-groups. As referenced in the table and FIG. 2, the first six bits a, b, c, d, e and i may form a first sub-block and the second four bits f, g, h and j may form a second sub-block corresponding to 5B6B encoder block 208 and 3B4B encoder block 206 respectively. An RD at the beginning of the 6-bit for first sub-block is the RD at the end of the last code-group. The RD at the beginning of the 4-bit or second sub-block corresponds to the RD at the end of the 6-bit sub-block. The RD at the end of the code-group corresponds to the RD at the end of the 4-bit sub-block.
The RD at the end of any sub-block is positive in instances where the sub-block contains more ones than zeros. The RD is also positive at the end of the 6-bit or first sub-block if the 6-bit sub-block is 000111. The RD is also positive at the end of the 4-bit or second sub-block whenever the 4-bit sub-block is 0011. The RD at the end of any sub-block may be negative in instances where the sub-block contains more zeros than ones. The RD may also be negative at the end of the 6-bit or first sub-block in cases where the 6-bit or first sub-block is 111000. Similarly, the RD is also negative at the end of the 4-bit or second sub-block whenever the 4-bit sub-block is 1100. In other instances, the RD at the end of the sub-block may be the same as at the beginning of the sub-block. In order to limit run length for both ones and zeros between the sub-blocks, sub-blocks that are encoded as 000111 or 0011 may be generated only when the RD at the beginning of the sub-block is positive. Accordingly, the RD at the end of these sub-blocks will also be positive. Likewise, sub-blocks that are encoded as 111000 or 1100 may be generated only when the RD at the beginning of the sub-block is negative. Accordingly, the RD at the end of these sub-blocks will also be negative.
On the transmitter side, during encoding, a transmitter or encoder will assume an initial negative RD. On the receiver side, a negative or positive RD may be assumed by the receiver. On the receiver side, during decoding, code-groups may be checked to determine their validity. If a current code-group is valid, the new RD will be generated. Since an RD must either be zero (0) or one (1), the RD may be utilized to check errors.
The stream of encoded data words transmitted across the link infrastructure 110, using a current running disparity encoding scheme, constitute a primary communication channel with a certain limited utilized information capacity.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the invention as set forth in the remainder of the present application with reference to the drawings.